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general description the max691a/max693a/max800l/max800m micro- processor (?) supervisory circuits are pin-compatible upgrades to the max691, max693, and max695. they improve performance with 30? supply current, 200ms typ reset active delay on power-up, and 6ns chip- enable propagation delay. features include write pro- tection of cmos ram or eeprom, separate watchdog outputs, backup-battery switchover, and a reset out- put that is valid with v cc down to 1v. the max691a/ max800l have a 4.65v typical reset-threshold voltage, and the max693a/max800ms?reset threshold is 4.4v typical. the max800l/max800m guarantee power-fail accuracies to ?%. ________________________applications computers controllers intelligent instruments automotive systems critical ? power monitoring ____________________________features 200ms power-ok/reset timeout period 1? standby current, 30? operating current on-board gating of chip-enable signals, 10ns max delay maxcap or supercap compatible guaranteed r r e e s s e e t t assertion to v cc = +1v voltage monitor for power-fail or low-battery warning power-fail accuracy guaranteed to ?% (max800l/m) available in 16-pin narrow so, plastic dip, and tssop packages ordering information max691a/max693a/max800l/max800m microprocessor supervisory circuits ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 reset reset wdo ce in gnd v cc v out vbatt top view max691a max693a max800l max800m ce out wdi pfo pfi osc sel osc in low line batt on dip/so/tssop pin configuration max691a max693a max800l max800m v out v cc batt on ce out ce in wdi pfo reset vbatt pfi gnd osc in osc sel 1 9 4 7 8 address decode audible alarm 5v regulator +8v 0.1 f cmos ram 2 12 11 10 15 13 5 3 a0-a15 i/o nmi reset p low line wdo system status indicators no connection 0.47f* 1n4148 *maxcap 614 typical operating circuit 19-0094; rev 8; 12/99 part max691a cue max691acpe 0 c to +70 c 0 c to +70 c temp. range pin-package 16 tssop 16 plastic dip max691ac/d max691aeje -40 c to +85 c 0 c to +70 c dice* 16 cerdip max691aeue max691aese -40 c to +85 c 0 c to +70 c 16 tssop 16 narrow so max691aepe -40 c to +85 c 16 plastic dip max691amje -55 c to +125 c 16 cerdip supercap is a registered trademark of baknor industries. maxcap is a registered trademark of the carborundum corp. max691acse 0 c to +70 c 16 narrow so ordering information continued on last page. *dice are specified at t a = +25 ?, dc parameters only. max691acwe 0 c to +70 c 16 wide so max691aewe -40 c to +85 c 16 wide so for free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. for small orders, phone 1-800-835-8769.
max691a/max693a/max800l/max800m microprocessor supervisory circuits 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (max691a, max800l: v cc = +4.75v to +5.5v; max693a, max800m: v cc = +4.5v to +5.5v; vbatt = 2.8v, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. terminal voltage (with respect to gnd) v cc .......................................................................-0.3v to +6v vbatt...................................................................-0.3v to +6v all other inputs .....................................-0.3v to (v out + 0.3v) input current v cc peak...........................................................................1.0a v cc continuous.............................................................250ma vbatt peak ..................................................................250ma vbatt continuous ..........................................................25ma gnd, batt on .............................................................100ma all other outputs ............................................................25ma continuous power dissipation (t a = +70 c) tssop (derate 6.70mw/ c above +70 c) ..................533mw narrow so (derate 8.70mw/ c above +70 c) ...........696mw wide so (derate 9.52mw/ c above +70 c)...............762mw plastic dip (derate 10.53mw/ c above +70 c) ..........842mw cerdip (derate 10.00mw/ c above +70 c) ..............800mw operating temperature ranges max69_ac_ _/max800_c_ _ .............................0 c to +70 c max69_ae_ _/max800_e_ _ ...........................-40 c to +85 c max69_amje ................................................-55 c to +125 c storage temperature range .............................-65 c to +160 c lead temperature (soldering, 10s) .................................+300 c vbatt - 0.15 max69_ac, max800_c 0.8 1.2 vbatt = 4.5v, i out = 20ma a -1.0 0.02 vbatt + 0.2v v cc vbatt standby current (note 3) -0.1 0.02 a 5 v cc < vbatt - 1.2v, vbatt = 2.8v supply current in battery-backup mode (excludes i out ) (note 2) vbatt = 2.8v, i out = 10ma v 0 5.5 conditions operating voltage range, v cc , vbatt (note 1) vbatt = 4.5v 0.04 1 a 30 100 supply current in normal operating mode (excludes i out ) v v out in battery-backup mode vbatt - 0.25 vbatt = 2.8v ? 30 vbatt - 0.3 vbatt-to-v out on-resistance units min typ max parameter 25 t a = +25 c v cc > vbatt - 1v t a = t min + t min vbatt = 2.0v, i out = 5ma t a = +25 c t a = t min + t min 15 vbatt = 2.0v v cc = 4.5v i out = 250ma v cc - 0.02 v cc - 0.05 i out = 25ma max69_ac/ae, max800_c/e i out = 210ma v cc - 0.2 v cc - 0.35 v cc - 0.2 v cc - 0.3 v v cc - 0.40 v cc - 0.17 v cc - 0.3v v out output max69_ae, max800_c/e max69_ac max69_a/m max69_ae, max800_e 0.8 1.4 max69_a/m 0.8 1.6 ? v cc = 4.5v v cc -to-v out on-resistance v vbatt - 0.3 power-up battery switchover threshold vbatt + 0.3 power-down
max691a/max693a/max800l/max800m microprocessor supervisory circuits _______________________________________________________________________________________ 3 max691a, max800l ma 720 reset output short-circuit current v 3.5 reset output voltage 0.1 0.4 0.004 0.3 ns 100 minimum watchdog input pulse width clock cycles 1024 watchdog timeout period, external clock (note 4) 4096 ms 70 100 140 watchdog timeout period, internal oscillator 1.0 1.6 2.25 clock cycles 2048 reset active timeout period, external clock (note 4) ms 140 200 280 reset active timeout period, internal oscillator ns 800 low line -to- reset delay s 80 v cc to reset delay max693a, max800m conditions mv 15 reset threshold hysteresis v 4.30 4.45 reset threshold voltage 4.55 4.70 4.25 4.40 4.50 4.50 4.65 4.75 units min typ max parameter output source current i source = 1.6ma, v cc = 5v i sink = 3.2ma, v cc = 4.25v i sink = 50a, v cc = 1v, vbatt = 0v, v cc falling v il = 0.8v, v ih = 0.75 x v cc short period long period short period long period max800m, t a = +25 c, v cc falling power-up power-up max800l, t a = +25 c, v cc falling power-down electrical characteristics (continued) (max691a, max800l: v cc = +4.75v to +5.5v; max693a, max800m: v cc = +4.5v to +5.5v; vbatt = 2.8v, t a = t min to t max , unless otherwise noted.) reset output voltage low (note 5) i sink = 3.2ma 0.1 0.4 v i sink = 3.2ma, v cc = 4.25v 0.4 low line output voltage i source = 1a, v cc = 5v 3.5 v low line output short-circuit current output source current 1 15 100 a i sink = 3.2ma 0.4 wdo output voltage i source = 500a, v cc = 5v 3.5 v wdo output short-circuit current output source current 310 ma v ih 0.75 x v cc wdi threshold voltage (note 6) v il 0.8 v wdi = 0v -50 -10 wdi input current wdi = v out 20 50 a sec mv 60 battery switchover hysteresis i sink = 25ma v 0.7 1.5 batt on output low voltage i sink = 3.2ma 0.1 0.4 source current a 1 15 100 batt on output short-circuit current sink current ma 60 reset and watchdog timer
max691a/max693a/max800l/max800m microprocessor supervisory circuits 4 _______________________________________________________________________________________ max69_ac/ae/am, v cc = 5v a 0.10 5 osc in leakage current s 12 reset-to- ce out delay 2.7 ce out output voltage high (reset active) 3.5 ns 610 ce in-to- ce out propagation delay (note 8) ma 0.1 0.75 2.0 ce out short-circuit current (reset active) ? 75 150 ce in-to- ce out resistance (note 7) a 0.005 1 ce in leakage current 60 pfi-to-pfo delay s 25 a 1 15 100 pfo output short-circuit current max800_c/e, v cc = 5v conditions 3.5 pfo output voltage v 0.4 na 0.01 25 pfi leakage current 1.225 1.25 1.275 pfi input threshold v 1.2 1.25 1.3 units min typ max parameter osc sel = 0v power-down v cc = 0v, vbatt = 2.8v, i out = 1a v cc = 5v, i out = -100a 50 ? source impedance driver, c load = 50pf disable mode, ce out = 0v enable mode disable mode i source = 1a, v cc = 5v i sink = 3.2ma v in = 20mv, v od = 15mv v in = -20mv, v od = 15mv output source current note 1: either v cc or vbatt can go to 0v, if the other is greater than 2.0v. note 2: the supply current drawn by the max691a/max800l/max800m from the battery excluding i out typically goes to 10a when (vbatt - 1v) < v cc < vbatt. in most applications, this is a brief period as v cc falls through this region. note 3: + = battery-discharging current, -- = battery-charging current. note 4: although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and do not vary with process or temperature. note 5: reset is an open-drain output and sinks current only. note 6: wdi is internally connected to a voltage divider between v out and gnd. if unconnected, wdi is driven to 1.6v (typ), disabling the watchdog function. note 7: the chip-enable resistance is tested with v cc = +4.75v for the max691a/max800l and v cc = +4.5v for the max693a/max800m. ce in = ce out = v cc / 2. note 8: the chip-enable propagation delay is measured from the 50% point at ce in to the 50% point at ce out. electrical characteristics (continued) (max691a, max800l: v cc = +4.75v to +5.5v; max693a, max800m: v cc = +4.5v to +5.5v; vbatt = 2.8v, t a = t min to t max , unless otherwise noted.) khz 50 osc in frequency range a 10 100 osc sel input pull-up current a 10 100 osc in input pull-up current osc sel = 0v osc sel = 0v osc sel = v out or floating, osc in = 0v v v out - 0.3 v out - 0.6 v ih 3.65 2.00 osc in external oscillator threshold voltage v il khz 100 osc in frequency with external capacitor osc sel = 0v, cosc = 47pf v power-fail comparator chip-enable gating internal oscillator
max691a/max693a/max800l/max800m microprocessor supervisory circuits _______________________________________________________________________________________ 5 36 26 -60 120 150 v cc supply current vs. temperature (normal operating mode) 34 max691a toc-01 temperature (?) v cc supply current ( a) 30 30 28 -30 0 90 32 60 v cc = 5v vbatt = 2.8v pfi, ce in = 0v 0 -60 120 150 battery supply current vs. temperature (battery-backup mode) 2 max691a toc-02 temperature ( c) battery supply current ( a) 30 1 0.5 -30 0 90 1.5 60 v cc = 5v vbatt = 2.8v no load 120 -60 120 150 180 chip-enable on-resistance vs. temperature 100 max691a toc-03 temperature ( c) ce on-resistance ( ? ) 30 60 40 -30 0 90 80 60 v cc = 4.75v vbatt = 2.8v v ce in = v cc /2 20 5 -60 120 150 vbatt to v out on-resistance vs. temperature max691a toc-04 temperature ( c) vbatt-to-v out on-resistance ( ? ) 30 10 -30 0 90 15 60 v cc = 0v vbatt = 2.8v vbatt = 2.0v vbatt = 4.5v 4.75 4.30 -60 120 150 reset threshold vs. temperature max691a toc-07 temperature ( c) reset threshold (v) 30 4.45 -30 0 90 4.65 4.40 4.35 4.50 4.70 4.55 4.60 60 vbatt = 2.8v max691a max800l max693a max800m 1.2 0.6 -60 120 150 v cc to v out on-resistance vs. temperature max691a toc-05 temperature ( c) v cc -to-v out on-resistance ( ? ) 30 0.8 -30 0 90 1.0 0.7 0.9 1.1 60 v cc = 5v, vbatt = 0v 1.50 0 -60 120 150 pfi threshold vs. temperature max691a toc-06 temperature ( c) pfi threshold (v) 30 0.50 -30 0 90 1.00 0.25 0.75 1.25 60 v cc = +5v, vbatt = 0v no load on pfo 600 0 -60 120 150 reset output resistance vs. temperature max691a toc-08 temperature ( c) reset output resistance ( ? ) 30 200 -30 0 90 100 500 300 400 60 v cc = 5v, vbatt = 2.8v sourcing current v cc = 0v, vbatt = 2.8v sinking current -60 120 150 reset delay vs. temperature 230 max691a toc-09 temperature ( c) reset delay (ms) 30 190 170 -30 0 90 210 220 180 200 60 v cc = 0v to 5v step vbatt = 2.8v __________________________________________typical operating characteristics (t a = +25 c, unless otherwise noted.)
max691a/max693a/max800l/max800m microprocessor supervisory circuits 6 _______________________________________________________________________________________ ____________________________typical operating characteristics (continued) (t a = +25 c, unless otherwise noted.) 20 0 0 battery current vs. input supply voltage 16 max691a toc-10 v cc (v) i batt ( a) 3 8 4 12 5 12 4 vbatt = 2.8v i out = 0a 100 0.1 watchdog and reset timeout period vs. osc in timing capacitor (cosc) 10 max691a toc-11 cosc (pf) watchdog and reset timeout period (sec) 100 1 10 1000 v cc = 5v vbatt = 2.8v long watchdog timeout period short watchdog timeout period reset active timeout period 0 300 chip-enable propagation delay vs. ce out load capacitance max691a toc-12 c load (pf) propagation delay (ns) 150 8 0 50 100 250 16 20 4 12 200 v cc = 5v ce in = 0v to 5v driver source impedance = 50 ? 1000 1 1 v cc to v out vs. output current (normal operating mode) 100 max691a toc-13 i out (ma) v cc to v out (mv) 100 10 10 1000 v cc = 4.5v vbatt = 0v slope = 0.8 ? 1000 1 vbatt to v out vs. output current (battery-backup mode) 100 max691a toc-14 i out (ma) vbatt to v out (mv) 10 10 1 100 v cc = 0v vbatt = 4.5v slope = 8 ? lo v cc to low line and ce out delay max691a toc-15 low line 5v v cc reset threshold lo hi hi hi lo ce out reset 12 s 800ns 80 s
max691a/max693a/max800l/max800m microprocessor supervisory circuits _______________________________________________________________________________________ 7 ______________________________________________________________pin description name function 1 vbatt battery-backup input. connect to external battery or capacitor and charging circuit. if backup battery is not used, connect to gnd. 2 v out output supply voltage. when v cc is greater than vbatt and above the reset threshold, v out connects to v cc . when v cc falls below vbatt and is below the reset threshold, v out connects to vbatt. connect a 0.1f capacitor from v out to gnd. connect v out to v cc if no backup battery is used. pin 3 v cc input supply voltage, 5v input. 4 gnd ground. 0v reference for all signals. 8 osc sel oscillator select. when osc sel is unconnected or driven high, the internal oscillator sets the reset delay and watchdog timeout period. when osc sel is low, the external oscillator input (osc in) is enabled (table 1). osc sel has a 10a internal pull-up. 7 osc in external oscillator input. when osc sel is unconnected or driven high, a 10a pull-up connects from v out to osc in, the internal oscillator sets the reset and watchdog timeout periods, and osc in selects between fast and slow watchdog timeout periods. when osc sel is driven low, the reset and watchdog timeout periods may be set either by a capacitor from osc in to ground or by an external clock at osc in (figure 3). 6 low line low line output goes low when v cc falls below the reset threshold. it returns high as soon as v cc rises above the reset threshold. 5 batt on battery on output. when v out switches to vbatt, batt on goes high. when v out switches to v cc, batt on goes low. connect the base of a pnp through a current-limiting resistor to batt on for v out current require- ments greater than 250ma. 13 ce in chip-enable input. the input to chip-enable gating circuit. if ce in is not used, connect ce in to gnd or v out. 12 ce out chip-enable output. ce out goes low only when ce in is low and v cc is above the reset threshold. if ce in is low when reset is asserted, ce out will stay low for 15s or until ce in goes high, whichever occurs first. 11 wdi watchdog input. wdi is a three-level input. if wdi remains either high or low for longer than the watchdog time- out period, wdo goes low and reset is asserted for the reset timeout period. wdo remains low until the next tran- sition at wdi. leaving wdi unconnected disables the watchdog function. wdi connects to an internal voltage divider between v out and gnd, which sets it to mid-supply when left unconnected. 10 pfo power-fail output. this is the output of the power-fail comparator. pfo goes low when pfi is less than 1.25v. this is an uncommitted comparator, and has no effect on any other internal circuitry. 9 pfi power-fail input. this is the noninverting input to the power-fail comparator. when pfi is less than 1.25v, pfo goes low. when pfi is not used, connect pfi to gnd or v out . 16 reset reset is an active-high output. it is open drain, and the inverse of reset . 15 reset reset output goes low whenever v cc falls below the reset threshold. reset will remain low typically for 200ms after v cc crosses the reset threshold on power-up. 14 wdo watchdog output. if wdi remains high or low longer than the watchdog timeout period, wdo goes low and reset is asserted for the reset timeout period. wdo returns high on the next transition at wdi. wdo remains high if wdi is unconnected. _______________detailed description r e s e t and reset outputs the max691a/max693a/max800l/max800m s reset and reset outputs ensure that the p (with reset inputs asserted either high or low) powers up in a known state, and prevents code-execution errors dur- ing power-down or brownout conditions. the reset output is active low, and typically sinks 3.2ma at 0.1v saturation voltage in its active state. when deasserted, reset sources 1.6ma at typically v out - 0.5v. reset output is open drain, active high, and typically sinks 3.2ma with a saturation voltage of 0.1v. when no backup battery is used, reset output is guaranteed to be valid down to v cc = 1v, and an external 10k ? pull-down resistor on reset insures that it will be valid with v cc down to gnd (figure 1). as v cc goes below 1v, the gate drive to the reset output switch reduces accordingly, increasing the r ds(on) and the saturation voltage. the 10k ? pull- down resistor insures the parallel combination of switch plus resistor is around 10k ? and the output saturation voltage is below 0.4v while sinking 40a. when using a 10k ? external pull-down resistor, the high state for reset output with v cc = 4.75v will be 4.5v typical. for battery voltages 2v connected to vbatt, reset and reset remain valid for v cc from 0v to 5.5v.
max691a/max693a/max800l/max800m reset and reset are asserted when v cc falls below the reset threshold (4.65v for the max691a/max800l, 4.4v for the max693a/max800m) and remain asserted for 200ms typ after v cc rises above the reset threshold on power-up (figure 5). the devices battery- switchover comparator does not affect reset assertion. however, both reset outputs are asserted in battery- backup mode since v cc must be below the reset threshold to enter this mode. watchdog function the watchdog monitors p activity via the watchdog input (wdi). if the p becomes inactive, reset and reset are asserted. to use the watchdog function, connect wdi to a bus line or p i/o line. if wdi remains high or low for longer than the watchdog time- out period (1.6sec nominal), wdo , reset, and reset are asserted (see reset and reset outputs section, and the watchdog output discussion on this page). watchdog input a change of state (high to low, low to high, or a mini- mum 100ns pulse) at the wdi during the watchdog period resets the watchdog timer. the watchdog default timeout is 1.6sec. to disable the watchdog function, leave wdi floating. an internal resistor network (100k ? equivalent imped- ance at wdi) biases wdi to approximately 1.6v. internal comparators detect this level and disable the watchdog timer. when v cc is below the reset thresh- old, the watchdog function is disabled and wdi is dis- connected from its internal resistor network, thus becoming high impedance. watchdog output the watchdog output ( wdo ) remains high if there is a transition or pulse at wdi during the watchdog timeout period. the watchdog function is disabled and wdo is a logic high when v cc is below the reset threshold, bat- tery-backup mode is enabled, or wdi is an open circuit. in watchdog mode, if no transition occurs at wdi during the watchdog timeout period, reset and reset are asserted for the reset timeout period (200ms typical). wdo goes low and remains low until the next transition at wdi (figure 2). if wdi is held high or low indefinitely, reset and reset will generate 200ms pulses every 1.6sec. wdo has a 2 x ttl output characteristic. selecting an alternative watchdog and reset timeout period the osc sel and osc in inputs control the watchdog and reset timeout periods. floating osc sel and osc in or tying them both to v out selects the nominal 1.6sec watchdog timeout period and 200ms reset timeout peri- od. connecting osc in to gnd and floating or connect- ing osc sel to v out selects the 100ms normal watchdog timeout delay and 1.6sec delay immediately after reset. the reset timeout delay remains 200ms (figure 2). select alternative timeout periods by con- necting osc sel to gnd and connecting a capacitor between osc in and gnd, or by externally driving osc in (table 1 and figure 3). osc in is internally connect- ed to a 100na (typ) current source that charges and discharges the timing capacitor to create the oscillator frequency, which sets the reset and watchdog timeout periods (see connecting a timing capacitor at osc in in the applications information section). microprocessor supervisory circuits 8 _______________________________________________________________________________________ max691a max693a to p reset 1k 15 reset wdi wdo reset t 1 t 1 t 3 t 2 t 1 = reset timeout period t 2 = normal watchdog timeout period t 3 = watchdog timeout period immediately after reset figure 1. adding an external pull-down resistor ensures r e s e t is valid with v cc down to gnd. figure 2. watchdog timeout period and reset active time
max691a/max693a/max800l/max800m microprocessor supervisory circuits _______________________________________________________________________________________ 9 chip-enable signal gating the max691a/max693a/max800l/max800m provide internal gating of chip-enable (ce) signals to prevent erroneous data from being written to cmos ram in the event of a power failure. during normal operation, the ce gate is enabled and passes all ce transitions. when reset is asserted, this path becomes disabled, prevent- ing erroneous data from corrupting the cmos ram. all these parts use a series transmission gate from ce in to ce out (figure 4). the 10ns max ce propagation delay from ce in to ce out enables the parts to be used with most ps. chip-enable input the chip-enable input ( ce in) is high impedance (dis- abled mode) while reset and reset are asserted. during a power-down sequence where v cc falls below the reset threshold or a watchdog fault, ce in assumes a high-impedance state when the voltage at ce in goes high or 15s after reset is asserted, whichever occurs first (figure 5). during a power-up sequence, ce in remains high impedance, regardless of ce in activity, until reset is deasserted following the reset timeout period. in the high-impedance mode, the leakage currents into this terminal are 1a max over temperature. in the low-impedance mode, the impedance of ce in appears as a 75 ? resistor in series with the load at ce out. the propagation delay through the ce transmission gate depends on both the source impedance of the drive to ce in and the capacitive loading on the chip- enable output ( ce out) (see chip-enable propagation delay vs. ce out load capacitance in the typical operating characteristics ). the ce propagation delay is production tested from the 50% point of ce in to the 50% point of ce out using a 50 ? driver and 50pf of load capacitance (figure 6). for minimum propagation delay, minimize the capacitive load at ce out, and use a low output-impedance driver. chip-enable output in the enabled mode, the impedance of ce out is equivalent to 75 ? in series with the source driving ce in. in the disabled mode, the 75 ? transmission gate is off and ce out is actively pulled to v out . this source turns off when the transmission gate is enabled. l o w l i n e output low line is the buffered output of the reset threshold comparator. low line typically sinks 3.2ma at 0.1v. for normal operation (v cc above the low line thresh- old), low line is pulled to v out . power-fail comparator the power-fail comparator is an uncommitted comparator that has no effect on the other functions of the ic. common uses include low-battery indication (figure 7), and early power-fail warning (see typical operating circuit ). power-fail input power fail input (pfi) is the input to the power-fail com- parator. it has a guaranteed input leakage of 25na max over temperature. the typical comparator delay is 25s from v il to v ol (power failing), and 60s from v ih to v oh (power being restored). if pfi is not used, con- nect it to ground. osc sel osc in 7 8 external oscillator osc sel osc in 7 8 external clock osc sel osc in 7 8 internal oscillator 100ms watchdog osc sel osc in 7 8 internal oscillator 1.6sec watchdog max691a max693a max800l max800m n.c. n.c. n.c. 50khz figure 3. oscillator circuits watchdog timeout period osc sel osc in normal immediately after reset reset timeout period low external clock input 1024 clks 4096 clks 2048 clks low external capacitor (600/47pf x c)ms (2.4/47pf x c)sec (1200/47pf x c)ms floating low 100ms 1.6sec 200ms floating floating 1.6sec 1.6sec 200ms table 1. reset pulse width and watchdog timeout selections
max691a/max693a/max800l/max800m microprocessor supervisory circuits 10 ______________________________________________________________________________________ max691a max693a max800l max800m chip-enable output control v cc 3 1 13 7 11 9 vbatt ce in osc in wdi pfi reset generator timebase for reset and watchdog watchdog transition detector watchdog timer 8 osc sel 1.25v gnd 4 4.65v* 6 low line 5 2 12 15 16 14 pfo wdo reset reset ce out 10 v out batt on * 4.4v for the max693a/max800m v cc ce in reset threshold ce out reset reset 100 s 15 s 100 s 5.0v 4.0v 5.0v 0v 5v 0v 5v 0v 0v 5v logic levels shown are from 0v to 5v. figure 4. max691a/max693a/max800l/max800m block diagram figure 5. reset and chip-enable timing
max691a/max693a/max800l/max800m microprocessor supervisory circuits ______________________________________________________________________________________ 11 power-fail output the power-fail output ( pfo ) goes low when pfi goes below 1.25v. it typically sinks 3.2ma with a saturation voltage of 0.1v. with pfi above 1.25v, pfo is actively pulled to v out . battery-backup mode two conditions are required to switch to battery-back- up mode: 1) v cc must be below the reset threshold, and 2) v cc must be below vbatt. table 2 lists the sta- tus of the inputs and outputs in battery-backup mode. battery on output the battery on (batt on) output indicates the status of the internal v cc /battery-switchover comparator, which controls the internal v cc and vbatt switches. for v cc greater than vbatt (ignoring the small hys- teresis effect), batt on typically sinks 3.2ma at 0.1v saturation voltage. in battery-backup mode, this termi- nal sources approximately 10a from v out . use batt on to indicate battery-switchover status or to supply base drive to an external pass transistor for higher-cur- rent applications (see typical operating circuit ). input supply voltage the input supply voltage (v cc ) should be a regulated 5v. v cc connects to v out via a parallel diode and a large pmos switch. the switch carries the entire cur- rent load for currents less than 250ma. the parallel diode carries any current in excess of 250ma. both the switch and the diode have impedances less than 1 ? each. the maximum continuous current is 250ma, but power-on transients may reach a maximum of 1a. max691a max693a max800l max800m ce in c load ce out gnd +5v 50 ? output impedance v cc vbatt 2.8v max691a max693a max800l max800m pfi pfo gnd +5v v cc vbatt 2.0v to 5.5v low batt figure 6. ce propagation delay test circuit figure 7. low-battery indicator pin name status 1 vbatt supply current is 1a max. 2 v out v out is connected to vbatt through an internal pmos switch. 3 v cc battery switchover comparator monitors v cc for active switchover. 4 gnd gnd 0v, 0v reference for all signals. 5 batt on logic high. the open-circuit output is equal to v out . 6 lowline logic low* 7 osc in osc in is ignored. 8 osc sel osc sel is ignored. 9 pfi the power-fail comparator remains active in the battery-backup mode for v cc vbatt - 1.2v typ. 10 pfo the power-fail comparator remains active in the battery-backup mode for v cc vbatt - 1.2v typ. below this volt- age, pfo is forced low. 11 wdi watchdog is ignored. 12 ce out logic high. the open-circuit voltage is equal to v out . 13 ce in high impedance 14 wdo logic high. the open-circuit voltage is equal to v out . 15 reset logic low* 16 reset high impedance* table 2. input and output status in battery-backup mode * v cc must be below the reset threshold to enter battery-backup mode.
max691a/max693a/max800l/max800m battery-backup input the battery-backup input (vbatt) is similar to the v cc input except the pmos switch and parallel diode are much smaller. accordingly, the on-resistances of the diode and the switch are each approximately 10 ? . continuous current should be limited to 25ma and peak currents (only during power-up) limited to 250ma. the reverse leakage of this input is less than 1a over temperature and supply voltage (figure 8). output supply voltage the output supply voltage (v out ) pin is internally con- nected to the substrate of the ic and supplies current to the external system and internal circuitry. all open- circuit outputs will, for example, assume the v out volt- age in their high states rather than the v cc voltage. at the maximum source current of 250ma, v out will typi- cally be 200mv below v cc . decouple this terminal with a 0.1f capacitor. __________applications information the max691a/max693a/max800l/max800m are not short-circuit protected. shorting v out to ground, other than power-up transients such as charging a decou- pling capacitor, destroys the device. all open-circuit outputs swing between v out and gnd rather than v cc and gnd. if long leads connect to the chip inputs, insure that these leads are free from ringing and other conditions that would forward bias the chip s protection diodes. there are three distinct modes of operation: 1) normal operating mode with all circuitry powered up. typical supply current from v cc is 35a while only leakage currents flow from the battery. 2) battery-backup mode where v cc is typically within 0.7v below vbatt. all circuitry is powered up and the supply current from the battery is typically less than 60a. 3) battery-backup mode where v cc is less than vbatt by at least 0.7v. vbatt supply current is 1a max. using supercap or maxcap with the max691a/max693a/max800l/max800m vbatt has the same operating voltage range as v cc , and the battery switchover threshold voltages are typi- cally 30mv centered at vbatt, allowing use of a supercap and a simple charging circuit as a backup source (figure 9). if v cc is above the reset threshold and vbatt is 0.5v above v cc , current flows to v out and v cc from vbatt until the voltage at vbatt is less than 0.5v above v cc . for example, with a supercap connected to vbatt and through a diode to v cc , if v cc quickly changes from 5.4v to 4.9v, the capacitor discharges through v out and v cc until vbatt reaches 5.1v typ. leakage current through the supercap charging diode and the internal power diode eventually discharges the supercap to v cc . also, if v cc and vbatt start from 0.1v above the reset threshold and power is lost at v cc , the supercap on vbatt dis- charges through v cc until vbatt reaches the reset threshold; then the battery-backup mode is initiated and the current through v cc goes to zero. microprocessor supervisory circuits 12 ______________________________________________________________________________________ max691a max693a max800l max800m vbatt v cc 0.1 f v out max691a max693a max800l max800m 1 0.47f* 1n4148 +5v 2 3 v cc gnd vbatt 4 v out * maxcap figure 8. v cc and vbatt to v out switch figure 9. supercap or maxcap on vbatt
using separate power supplies for vbatt and v cc if using separate power supplies for v cc and vbatt, vbatt must be less than 0.3v above v cc when v cc is above the reset threshold. as described in the previ- ous section, if vbatt exceeds this limit and power is lost at v cc , current flows continuously from vbatt to v cc via the vbatt-to-v out diode and the v out -to-v cc switch until the circuit is broken (figure 8). alternate chip-enable gating using memory devices with both ce and ce inputs allows the ce loop to be bypassed. to do this, con- nect ce in to ground, pull up ce out to v out , and connect ce out to the ce input of each memory device (figure 10). the ce input of each part then connects directly to the chip-select logic, which does not have to be gated. adding hysteresis to the power-fail comparator hysteresis adds a noise margin to the power-fail com- parator and prevents repeated triggering of pfo when v in is near the power-fail comparator trip point. figure 11 shows how to add hysteresis to the power-fail com- max691a/max693a/max800l/max800m microprocessor supervisory circuits ______________________________________________________________________________________ 13 max691a max693a max800l max800m v out gnd ce in ce ce ce out ce ce ce ce ce ce *maximum rp value depends on the number of rams. minimum rp value is 1k ?. active-high ce lines from logic ram 1 ram 2 ram 3 ram 4 rp* max691a max693a max800l max800m v cc gnd pfi *optional r2 r3 r1 v in +5v c1* to p pfo v trip = 1.25 r1 + r2 r2 v h = 1.25/ r2 i i r3 v l - 1.25 + 5 - 1.25 = 1.25 r1 + r2 i i r3 r1 r3 r2 pfo 5v 0v 0v v h v trip v in v l max691a max693a max800l max800m v cc gnd pfi r2 r1 +5v pfo pfo 5v 0v note : v trip is negative. 0v v trip v- 5 - 1.25 = 1.25 - v trip r1 r2 v- figure 10. alternate ce gating figure 12. monitoring a negative voltage figure 11. adding hysteresis to the power-fail comparator
max691a/max693a/max800l/max800m microprocessor supervisory circuits 14 ______________________________________________________________________________________ parator. select the ratio of r1 and r2 such that pfi sees 1.25v when v in falls to the desired trip point (v trip ). resistor r3 adds hysteresis. it will typically be an order of magnitude greater than r1 or r2. the current through r1 and r2 should be at least 1a to ensure that the 25na (max) pfi input current does not shift the trip point. r3 should be larger than 10k ? to prevent it from loading down the pfo pin. capacitor c1 adds noise rejection. monitoring a negative voltage the power-fail comparator can be used to monitor a negative supply voltage using figure 12 s circuit. when the negative supply is valid, pfo is low. when the neg- ative supply voltage drops, pfo goes high. this cir- cuit s accuracy is affected by the pfi threshold tolerance, the v cc voltage, and resistors r1 and r2. backup-battery replacement the backup battery may be disconnected while v cc is above the reset threshold. no precautions are neces- sary to avoid spurious reset pulses. negative-going v cc transients while issuing resets to the p during power-up, power- down, and brownout conditions, these supervisors are relatively immune to short-duration, negative-going v cc transients (glitches). it is usually undesirable to reset the p when v cc experiences only small glitches. figure 13 shows maximum transient duration vs. reset- comparator overdrive, for which reset pulses are not generated. the graph was produced using negative- going v cc pulses, starting at 5v and ending below the reset threshold by the magnitude indicated (reset com- parator overdrive). the graph shows the maximum pulse width a negative-going v cc transient may typical- ly have without causing a reset pulse to be issued. as the amplitude of the transient increases (i.e., goes far- ther below the reset threshold), the maximum allowable pulse width decreases. typically, a v cc transient that goes 100mv below the reset threshold and lasts for 40s or less will not cause a reset pulse to be issued. a 100nf bypass capacitor mounted close to the v cc pin provides additional transient immunity. connecting a timing capacitor at osc in when osc sel is connected to ground, osc in dis- connects from its internal 10a (typ) pull-up and is internally connected to a 100na current source. when a capacitor is connected from osc in to ground (to select alternative reset and watchdog timeout peri- ods), the current source charges and discharges the timing capacitor to create the oscillator that controls the reset and watchdog timeout period. to prevent timing errors or oscillator start-up problems, minimize external current leakage sources at this pin, and locate the capacitor as close to osc in as possible. the sum of pc-board leakage plus osc capacitor leakage must be small compared to 100na. 100 0 10 1000 10000 40 20 80 60 max791-16 reset comparator overdrive, (reset threshold voltage - v cc ) (mv) maximum transient duration ( s) 100 v cc = 5v t a = +25? 0.1 f capacitor from v out to gnd figure 13. maximum transient duration without causing a reset pulse vs. reset comparator overdrive
max691a/max693a/max800l/max800m microprocessor supervisory circuits ______________________________________________________________________________________ 15 maximum v cc fall time the v cc fall time is limited by the propagation delay of the battery switchover comparator and should not exceed 0.03v/s. a standard rule of thumb for filter capacitance on most regulators is on the order of 100f per amp of current. when the power supply is shut off or the main battery is disconnected, the associated initial v cc fall rate is just the inverse or 1a/100f = 0.01v/s. the v cc fall rate decreases with time as v cc falls expo- nentially, which more than satisfies the maximum fall-time requirement. watchdog software considerations a way to help the watchdog timer keep a closer watch on software execution involves setting and resetting the watchdog input at different points in the program, rather than pulsing the watchdog input high-low-high or low-high-low. this technique avoids a stuck loop where the watchdog timer continues to be reset within the loop, keeping the watchdog from timing out. figure 14 shows an example flow diagram where the i/o dri- ving the watchdog input is set high at the beginning of the program, set low at the beginning of every subrou- tine or loop, then set high again when the program returns to the beginning. if the program should hang in any subroutine, the i/o is continually set low and the watchdog timer is allowed to time out, causing a reset or interrupt to be issued. start set wdi low return end subroutine or program loop set wdi high figure 14. watchdog flow diagram
max691a/max693a/max800l/max800m microprocessor supervisory circuits 16 ______________________________________________________________________________________ microprocessor supervisory circuits ordering information (continued) part max693a cue max693acse max693acpe 0 c to +70 c 0 c to +70 c 0 c to +70 c temp. range pin-package 16 tssop 16 narrow so 16 plastic dip max693ac/d max693aeje -40 c to +85 c 0 c to +70 c dice* 16 cerdip max693aeue max693aewe -40 c to +85 c -40 c to +85 c 16 tssop 16 wide so max693aepe -40 c to +85 c 16 plastic so max693amje -55 c to +125 c 16 cerdip max800l cue max800lcse max800leue -40 c to +85 c 0 c to +70 c 0 c to +70 c 16 tssop 16 narrow so 16 tssop max800lepe max800m cue max800mcse -40 c to +85 c 16 plastic dip max800meue -40 c to +85 c 0 c to +70 c 0 c to +70 c 16 tssop 16 narrow so 16 tssop max800mepe -40 c to +85 c 16 plastic dip * dice are specified at t a = +25?, dc parameters only. ___________________chip topography wdi ce in ce out v cc gnd wdo batt on low line v out vbatt reset reset pfi pfo osc sel osc in 0.11" (2.794mm) 0.07" (1.778mm) transistor count: 729 substrate connected to v out max693acwe 0 c to +70 c 16 wide so max693aese -40 c to +85 c 16 narrow so max800mese -40 c to +85 c 16 narrow so max800mcpe 0 c to +70 c 16 plastic dip max800lese -40 c to +85 c 16 narrow so max800lcpe 0 c to +70 c 16 plastic dip
max691a/max693a/max800l/max800m microprocessor supervisory circuits ______________________________________________________________________________________ 17 ________________________________________________________package information tssop.eps
max691a/max693a/max800l/max800m microprocessor supervisory circuits 18 ______________________________________________________________________________________ ___________________________________________package information (continued) soicn.eps
max691a/max693a/max800l/max800m microprocessor supervisory circuits ______________________________________________________________________________________ 19 soicw.eps ___________________________________________package information (continued)
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 ? 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products. max691a/max693a/max800l/max800m microprocessor supervisory circuits notes

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